Improved active device isolation techniques are required in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 5,677,234, 5,750,433, 5,753,562, 5,837,595, 5,858,842 and 5,885,883.
But, such techniques as LOCOS may not be appropriate for current high integration devices because they typically result in the formation of isolation regions having bird's beak oxide extensions which may consume relatively large amounts of area and thereby impede attempts for higher integration levels. To address this and other problems, STI techniques have been developed. One such technique is illustrated by FIGS. 1A-1E. In particular, FIG. 1A illustrates the steps of forming a pad oxide layer 3, a pad nitride layer 4, a high temperature oxide (HTO) layer 5 and an anti-reflective layer 6 on a semiconductor substrate 2. A photoresist layer 10 is then patterned on the anti-reflective layer 6. A trench mask 8 is then formed by performing an etching step using the patterned photoresist layer 10 as an etching mask. As illustrated by FIG. 1B, another etching step is then performed to define a trench 12 in the substrate 2, using the trench mask 8 as a etching mask. During the etching step, the anti-reflective layer 6 may also be removed.
Referring now to FIG. 1C, a thermal oxide layer 14 is then formed in the trench to remove etching damage. A trench isolation layer comprising an undoped silicate glass (USG) layer 15 and a PE-TEOS oxide layer 16 (for reducing stress in the USG layer), is then formed to fill the trench 12. As illustrated by FIG. 1D, a planarization step (e.g., CMP) is then performed, using the pad nitride layer 4 as an etch stop layer. Then, as illustrated by FIG. 1E, the pad nitride layer 4 and pad oxide layer 3 are sequentially removed to define a trench isolation region 18.
Unfortunately, because the substrate 2 may have a substantially different coefficient of thermal expansion than the USG layer 15 in the trench 12, substantial stresses may develop in the substrate 2 during back-end processing. These stresses may adversely influence the device characteristics of active devices formed in active regions adjacent the trench isolation region 18. The subsequent formation of an oxide layer on the active regions (e.g., gate oxide layers) may also act to increase the degree of stress in the substrate 2, due to volume expansion in the trench isolation region 18. Grain dislocation defects may also be generated at the bottom corners and sidewalls of the trench in response to the volume expansion. Such defects may lead to increases in junction leakage currents in adjacent active devices, and decreases in reliability and yield.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming field oxide isolation regions.